Alacsonyabb ár! AD7606 adatgyűjtő modul 16b szinkronizáció 200Ksps Nagyobb

AD7606 adatgyűjtő modul 16b szinkronizáció 200Ksps

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6 265 Ft‎

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6 737 Ft‎

Egyéb infó

]
OS2 OS1 OS2: a combination of state selection oversampling mode.
000 means no oversampling, the maximum sampling rate of 200ksps.
001 represents two times oversampling, which is the hardware inside collected two samples averaging
010 represents four times oversampling, which is the hardware inside collect four samples averaged
011 represents eight times oversampling, which is the hardware inside collected eight samples averaged
100 represents 16 times oversampling, which is the hardware inside collected 16 samples averaged
101 represents 32 times oversampling, which is an internal hardware averaging collected 32 samples
110 represents 64 times oversampling, which is the hardware inside collected 64 samples averaged
Oversampling ratio is higher, the longer the ADC conversion time, the lower the maximum sampling frequency can be obtained.
CVA, CVB: AD conversion start control signal channel 1-4 decision CVA, CVB decided 5-8 channels.
Two signals can stagger a short time, in general, can be CVA, CVB parallel together.
RAGE: Select the range of 0 means plus or minus 5V, 1 indicates negative 10V.
RD: Read signal
RST: Reset signal
Busy: Busy Signal
CS: chip-select signal
FRST: first a channel samples indicating signal
VIO: communication interface level
DB0 - DB15: Data Bus
[16 parallel mode wiring diagram --- AD7606 also supports 8-bit bus mode, see the AD7606 data sheet
MCU side AD7606 module
GND <----- ground
+5 V <----- 5V power supply
RAGE <----- can also be connected to the GPIO connected fixed level
OS2 <----- can also be connected to the GPIO connected fixed level
OS1 <----- can also be connected to the GPIO connected fixed level
OS0 <----- can also be connected to the GPIO connected fixed level
CVA <----- access the GPIO (output) is used to start AD conversion [Recommended pick pin with PWM output capability]
CVB <--- |
RD <----- 8080 bus read signal NOE
RST <----- GPIO output hardware reset AD606
Busy -----> GPIO input AD606 being converted instructions. [Recommended connection with external pin interrupt capability]
CS <----- 8080 bus chip select NCS
VIO <----- microcontroller power supply
DB0-DB15 -----> 8080 data bus (16)
FRST may take
[SPI interface mode wiring diagram
MCU side AD7606 module
GND <----- ground
+5 V <----- 5V power supply
RAGE <----- any output GPIO, can be accessed by a fixed level
OS2 <----- any output GPIO, can be accessed by a fixed level
OS1 <----- any output GPIO, can be accessed by a fixed level
OS0 <----- any output GPIO, can be accessed by a fixed level
CVA <----- access the GPIO (output) is used to start AD conversion [Recommended pick pin with PWM output capability]
CVB <--- |
RD / SCLK <----- SPI bus clock SCK
RST <----- any output GPIO, for hardware reset AD606
Busy -----> GPIO input, AD606 being converted instructions. [Recommended connection with external pin interrupt capability]
CS <----- SPI bus chip select SCS
VIO <----- microcontroller power supply
DB7 (DOUTA) -----> SPI bus data lines MISO
DB14 - DB15 may pick
FRST may take
Software implementations [1] --- timing acquisition of SPI example we offer document using this program, see bsp_spi_ad7606.c
In the timer interrupt service routine implementation:
Timer interrupt ISR:
{
Interrupt entry
AD7606 DATA Acquisition Module 16Bits ADC 8CH Synchronization 200Ksps

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